Generally, a plurality of cells including such unit devices as transistors, capacitors and the like are integrated over a limited area according to a size of a semiconductor device. For independent operational characteristics of the cells, electrical isolation is necessary. To achieve the electrical isolation between cells, LOCOS (local oxidation of silicon) or STI (shallow trench isolation) may be used. In LOCOS, a silicon substrate is recessed and a field oxide layer is then grown in the recess. In STI, a trench is formed by vertically etching a silicon substrate, and the trench is filled with an insulator.
In a LOCOS device, the field oxide layer may expand into an active area to generate a bird's beak from an edge part of the field oxide layer. Hence, LOCOS has the disadvantage that the size of the active area is decreased. Conversely, in STI, a narrow and deep trench is formed by dry etch such as reactive ion etch, plasma etch and the like. The trench is filled with an insulating layer, whereby the problem of bird's beak does not arise. In STI the surface of the trench filled with the insulating layer is planarized. And, STI has an advantage in downsizing a semiconductor device due to the relatively small size of the device isolation area. Therefore, a device isolation layer may be formed by STI in a 90 nm-scale semiconductor device.
A method of forming an isolation layer in a semiconductor device according to a related art is explained with reference to the accompanying drawings as follows. FIGS. 1A to 1E are cross-sectional diagrams of a method of forming an isolation layer in a semiconductor device using STI according to the related art. Referring to FIG. 1A, a buffer oxide layer 12, a pad nitride layer 13 and a TEOS oxide layer 14 may be sequentially formed over a p-type semiconductor substrate 11. A photoresist layer 15 may be formed over the TEOS oxide layer 14.
The pad nitride layer 13 plays a role as a mask in etching a semiconductor substrate for a device isolation area and also plays a role as an etch stopper in CMP (chemical mechanical polishing) process. Hence, the pad nitride layer 13 may be formed about 1,000 Å thick by LPCVD in a 90 nm-scale semiconductor device.
Referring to FIG. 1B, the photoresist layer 15 may be patterned by performing exposure and development on the photoresist layer 15 using a mask. The photoresist layer 15 remains in an active area but is removed from a device isolation area. The TEOS oxide layer 14, the pad nitride layer 13 and the buffer oxide layer 12 are etched using the patterned photoresist layer 15 as a mask, whereby the p-type semiconductor substrate 11 is partially exposed. Subsequently, a trench 16 is formed by etching the exposed p-type semiconductor substrate 11 to a prescribed depth.
Referring to FIG. 1C, the remaining photoresist layer 15 is removed. An HDP (high density plasma) oxide layer 18 is deposited over the substrate until the trench 16 is sufficiently filled with the HDP oxide layer 18.
Referring to FIG. 1D, a device isolation layer 18a is formed within the trench 16 by removing the HDP oxide layer 18 and the TEOS oxide layer 14 by CMP (chemical mechanical polishing) until a surface of the pad nitride layer 13 is exposed.
Referring to FIG. 1E, the pad nitride layer 13 and the pad oxide layer 12 are removed. Finally, a specific semiconductor device is fabricated by performing necessary processes for gate electrode formation, impurity ion implantation and the like. However, the related art device isolation method for a semiconductor device has problems.
As mentioned above, the pad nitride layer plays a role as a mask in etching the semiconductor substrate of the device isolation area and also plays a role as an etch stopper in CMP. As the pad nitride layer deposited by LPCVD becomes thinner, the trench can be more sufficiently filled up with the HDP oxide layer to enhance the device isolation characteristic. Yet, if the pad nitride layer deposited by LPCVD gets thinner, more stress is applied to the pad nitride layer. Hence, the thickness of the pad nitride layer should be maintained as about 1,000 Å for at least the limited margin of the thickness. Therefore, in the related art device isolation forming method, the gap filling characteristics of the HDP oxide layer are limited, limiting the enhancement of device isolation characteristics.